74HC595 是一款漏極開路輸出的CMOS 移位寄存器，輸出端口為可控的三態(tài)輸出 端，亦能串行輸出控制下一級級聯(lián)芯片。
74HC595特點(diǎn)：
高速移位時鐘頻率Fmax>25MHz
標(biāo)準(zhǔn)串行（SPI）接口
CMOS 串行輸出，可用于多個設(shè)備的級聯(lián)
低功耗：TA =25℃時，Icc=4μA（MAX）
圖1 74HC595引腳圖
74HC595引腳功能表：
|
管腳編號 |
管腳名 |
管腳定義功能 |
|
1、2、3、4、5、6、7、15 |
QA—QH |
三態(tài)輸出管腳 |
|
8 |
GND |
電源地 |
|
9 |
SQH |
串行數(shù)據(jù)輸出管腳 |
|
10 |
SCLR |
移位寄存器清零端 |
|
11 |
SCK |
數(shù)據(jù)輸入時鐘線 |
|
12 |
RCK |
輸出存儲器鎖存時鐘線 |
|
13 |
OE |
輸出使能 |
|
14 |
SI |
數(shù)據(jù)線 |
|
15 |
VCC |
電源端 |
圖2 74HC595邏輯圖
74HC595真值表：
|
輸入管腳 |
輸出管腳 | ||||
|
SI |
SCK |
SCLR |
RCK |
OE | |
|
X |
X |
X |
X |
H |
QA—QH 輸出高阻 |
|
X |
X |
X |
X |
L |
QA—QH 輸出有效值 |
|
X |
X |
L |
X |
X |
移位寄存器清零 |
|
L |
上沿 |
H |
X |
X |
移位寄存器存儲L |
|
H |
上沿 |
H |
X |
X |
移位寄存器存儲H |
|
X |
下沿 |
H |
X |
X |
移位寄存器狀態(tài)保持 |
|
X |
X |
X |
上沿 |
X |
輸出存儲器鎖存移位寄存器中的狀態(tài)值 |
|
X |
X |
X |
下沿 |
X |
輸出存儲器狀態(tài)保持 |
74HC595參數(shù):
Absolute Maximum Ratings絕對最大額定值
|
參數(shù) |
數(shù)值 |
|
Supply Voltage電源電壓(VCC) |
−0.5 to +7.0V |
|
DC Input Voltage 直流輸入電壓(VIN) |
−1.5 to VCC +1.5V |
|
DC Output Voltage 直流輸出電壓(VOUT) |
−0.5 to VCC +0.5V |
|
Clamp Diode Current 鉗位二極管電流(IIK, IOK) |
±20mA |
|
DC Output Current直流輸出電流，每個引腳（輸出） |
±35mA |
|
DC VCC or GND Current,per pin (ICC) |
±70mA |
|
Storage Temperature Range 儲存溫度范圍(TSTG) |
−65℃ to +150℃ |
|
Power Dissipation 功耗(PD) | |
|
(Note 3) |
600mW |
|
S.O. Package only |
500mW |
|
Lead Temperature (TL) (Soldering 10 seconds) |
260℃ |
Recommended Operating Conditions建議操作條件
|
參數(shù) |
最小 |
最大 |
單位 |
|
Supply Voltage電源電壓(VCC) |
2 |
6 |
v |
|
DC Input or Output Voltage(VIN, VOUT)輸入輸出電壓 |
0 |
VCC |
V |
|
Operating Temperature Range工作溫度范圍 (TA) |
−40 |
+85 |
℃ |
|
Input Rise or Fall Times 輸入上升或下降時間 | |||
|
(tr,tf) VCC = 2.0V |
- |
1000 |
ns |
|
VCC = 4.5V |
- |
500 |
ns |
|
VCC = 6.0V |
- |
400 |
ns |
DC SPECIFICATIONS直流電氣規(guī)格
|
Symbol 符號 |
Parameter 參數(shù) |
Conditions 條件 |
VCC |
TA=25℃ |
TA= −40to85℃ |
TA= −55to125℃ |
UNIT 單位 | |
|
典型 |
Guaranteed Limits保證界限 | |||||||
|
VIH |
Minimum High Level Input Voltage最大高電平輸入電壓 |
- |
2.0V |
- |
1.5 |
1.5 |
1.5 |
V |
|
4.5V |
- |
3.15 |
3.15 |
3.15 | ||||
|
6.0V |
- |
4.2 |
4.2 |
4.2 | ||||
|
VIL |
Maximum LOW Level Input Voltage最大低電平輸入電壓 |
- |
2.0V |
- |
0.5 |
0.5 |
0.5 |
V |
|
4.5V |
- |
1.35 |
1.35 |
1.35 | ||||
|
6.0V |
- |
1.8 |
1.8 |
1.8 | ||||
|
VOH |
Minimum HIGH Level Output Voltage最大高電平輸出電壓 |
VIN=VIH or VIL|IOUT|≤20μA |
2.0V |
2.0 |
1.9 |
1.9 |
1.9 |
V |
|
4.5V |
4.5 |
4.4 |
4.4 |
4.4 | ||||
|
6.0V |
6.0 |
5.9 |
5.9 |
5.9 | ||||
|
Q'H |
VIN = VIH or VIL |
V | ||||||
|
|IOUT| ≤4.0mA |
4.5V |
4.2 |
3.98 |
3.84 |
3.7 | |||
|
|IOUT| ≤5.2mA |
6.0V |
5.2 |
5.48 |
5.34 |
5.2 | |||
|
QA thru QH |
VIN = VIH or VIL |
V | ||||||
|
|IOUT| ≤6.0mA |
4.5V |
4.2 |
3.98 |
3.84 |
3.7 | |||
|
IOUT| ≤ 7.8mA |
6.0V |
5.7 |
5.48 |
5.34 |
5.2 | |||
|
VOL |
Maximum LOW Level Output Voltage最大低電平輸出電壓 |
VIN=VIH or VIL|IOUT| ≤ 20μA |
2.0V |
0 |
0.1 |
0.1 |
0.1 |
V |
|
4.5V |
0 |
0.1 |
0.1 |
0.1 | ||||
|
6.0V |
0 |
0.1 |
0.1 |
0.1 | ||||
|
Q'H |
VIN = VIH or VIL |
V | ||||||
|
|IOUT| ≤ 4mA |
4.5V |
0.2 |
0.26 |
0.33 |
0.4 | |||
|
|IOUT| ≤5.2mA |
6.0V |
0.2 |
0.26 |
0.33 |
0.4 | |||
|
QA thru QH |
VIN = VIH or VIL |
V | ||||||
|
|IOUT| ≤6.0mA |
4.5V |
0.2 |
0.26 |
0.33 |
0.4 | |||
|
|IOUT| ≤7.8mA |
6.0V |
0.2 |
0.26 |
0.33 |
0.4 | |||
|
IIN |
Maximum Input Current最大輸入電流 |
VIN=VCC or GND |
6.0V |
- |
±0.1 |
±1.0 |
±1.0 |
μA |
|
IOZ |
Maximum 3-STATE Output Leakage最大3態(tài)輸出泄漏電流 |
VOUT = VCC or GND G = VIH |
6.0V |
- |
±0.5 |
±5.0 |
±10 |
μA |
|
ICC |
Maximum Quiescent Supply Current電源電流 |
VIN=VCC or GND IOUT = 0μA |
6.0V |
- |
8.0 |
80 |
160 |
μA |
交流電氣特性：
|
Symbol 符號 |
Parameter 參數(shù) |
Conditions 條件 |
典型 |
Guaranteed Limit |
UNIT 單位 |
|
fMax |
最高工作頻率 |
- |
50 |
30 |
MHz |
|
tPHL, tPLH |
Maximum Propagation Delay,最大傳輸延遲 SCK to Q’ H |
CL = 45 pF |
12 |
20 |
ns |
|
tPHL, tPLH |
Maximum Propagation Delay, 最大傳輸延遲RCK to QA thru QH |
CL = 45 pF |
18 |
30 |
ns |
|
tPZH, tPZL |
Maximum Output Enable Time from G to QA thru QH 最大輸出啟用時間G to QA thru QH |
RL=1kΩ CL=45pF |
17 |
28 |
ns |
|
tPHZ, tPLZ |
Maximum Output Disable Time from G to QA thru QH最大輸出禁用時間G to QA thru QH |
RL=1kΩ CL=5pF |
15 |
25 |
ns |
|
tS |
Minimum Setup Time from SER to SCK |
- |
- |
20 |
ns |
|
tS |
Minimum Setup Time from SCLR to SCK |
- |
- |
20 |
ns |
|
tS |
Minimum Setup Time from SCK to RCK |
- |
- |
40 |
ns |
|
tH |
Minimum Hold Time from SER to SCK |
- |
- |
0 |
ns |
|
tW |
Minimum Pulse Width of SCK or RCK |
- |
- |
16 |
ns |
圖3 74HC595 時序圖圖
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